Extended Software Development Workshop: high performance computing for simulation of complex phenomena
Methods for simulating complex phenomena are increasingly becoming an accepted mean of pursuing scientific discovery. Especially in molecular sciences, simulation methods have a key role. They allow to perform virtual experiments and to estimate observables of interest for a wide range of complex phenomena such as proteins conformational changes, reactions and protein-ligand binding processes. Means to achieve these goals are continuum modeling (e.g. Poisson-Boltzmann equation1), meso-scale methods2 or more accurate full atomistic simulations either classical3 or at quantum level of theory4. All these techniques have the common requirements of solving complex equations that call for adequate computing resources.
Modern computing units are inherently parallel machines where multiple multi-core CPUs often paired with one or many accelerators such as GPUs or, more recently, FPGA devices. In this context, High performance computing (HPC) is the computer science discipline that specifically addresses the task of optimizing the performance of software through code refactoring, single/multi thread/process optimization. Despite several excellent codes already exist, the requirement of properly accelerating simulative codes is still compelling with several engines not leveraging the actual capabilities of current architectures.
The aim of this E-CAM Extended Software Development Workshop (ESDW) is to introduce the participants to HPC through frontal lessons on computer architectures, applications and via hands-on sessions where participants will plan a suitable optimization strategy for one of the selected codes and start optimizing its performance.
This ESDW will thus focus on the technological aspects in HPC optimization/parallelization procedures. It will be a virtual meeting to facilitate participation, and the workshop will last one week (5 days).
The primary goal of the workshop will be to show to the participants which are the main challenges in code optimization and parallelization and the correct balance between code readability, long term maintenance and performance. This will include technical lessons in which parallelization paradigms are explained in detail. A second goal will be to allow participants to find computational bottlenecks within software and to setup an optimization/parallelization strategy including some initial optimization on the selected codes. This activity will be interleaved with talks that present examples of HPC oriented applications through invited speakers.
The lessons will cover:
- Modern computing machinery architectures
- Code refactoring and single thread optimizations
- Shared memory architectures and parallelization
- Multi-process parallelization
- GPU oriented parallelization
We will select one/two codes among the ones proposed by the applicants during the registration procedure. Each applicant can apply either proposing a code or not. Codes selection will be based on the code quality, wide interest for the ECAM Community and the commitment of the proposers to carry on (IIT HPC group will support this activity) a long term optimization project beyond the ECAM workshop timeframe.
We will issue a first call for codes-bringing applicants and for codes-agnostic applicants that will participate irrespectively of the selected codes. Then, once the one/two codes are selected a second call will be issued for applicants only. Applicants proposing a code are supposed to know in detail the software internals, its usage and to have prepared proper testing/benchmarking input files; codes can be in C/C++/Fortran or even in Python for an initial porting. Ideally, the code should be serial in order to plan a full optimization strategy. All the attendees will remotely access the IIT Cluster (64 nodes, GPUs equipped) during the hands-on sessions.
Andrea Cavalli (Italian Institute of Technology) - Organiser
Sergio Decherchi (Fondazione Istituto Italiano di Tecnologia) - Organiser
Marco Ferrarotti (Istituto Italiano di Tecnologia) - Organiser
Walter Rocchia (Istituto Italiano di Tecnologia) - Organiser